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17 Jun 2019 
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Keywords—Resistor string; Digital-to-Analog Converter (DAC); phones applications.
I. INTRODUCTION
A device that converts discrete digital binary code into a continuous varying analog signal. DAC is implemented as integrated circuits. DACs are normally used in music players to convert digital audio signals into analog audio signals. And also used in televisions and mobile phones to convert digital video data into analog video signals [1].
The DAC converter is used in phones to convert a digital audio signal into an analog audio signal, as we know We can\’t hear a digital audio and ours phones can\’t store analog audio, so the Audio signal is converted into a digital copy because it\’s easier to compress and stored. Therefore, when we play our music for example, it has to pass through a DAC to get the analog signal.
The suitability of a DAC for a particular application is determined by tradeoff among six main parameters: physical size, power consumption, resolution, speed, accuracy, cost. 3-bit Resistor String DAC is formed of a series of resistors, which are connected to an OPAMP buffer through an analog multiplexer. Based on the digital inputs, the switch multiplexer selects the corresponding voltage from the resistor string (which acts as voltage divider within the referenced voltage range) and gives it to the Opamp buffer, which simply buffers the signal to drive a high capacity load.
Based on the inputs and design specifications, schematics and layout for different blocks of DAC mentioned above are designed in Cadence Custom IC Design Tools using 130-nm CMOS process. Schematic simulation and Post-Layout simulations are tabulated and the designed DAC\’s static performance parameters such as Integral Non-Linearity (INL), Differential Non-Linearity (DNL), Gain Error, Offset Error with Power and Area of design are measured using Cadence [1]-[2]-[3].
II. CIRCUIT DESIGN
The proposed 3-bit Resistor String DAC is shown in figure 1, which are connected to an OPAMP buffer through an analog multiplexer. Based on the
Figure 1. Proposed 3-bits DAC structure
A. Two-Stage CMOS OPAMP Buffer
• Differential Input Gain Stage: Transistors M1, M2, M3, M4 and M5 form the first stage of the op amp. The gate of M1 is the non-inverting input and of M2 is the inverting input. A discriminating input signal is applied across the two input terminals will be amplified according to the gain of the differential stage. Transistors M3 and M4 constitute high force current mirrors. The current mirror topology performs the differential to single- ended conversion of the input signal. The current from M1 is mirrored by M3 and M4 and subtracted from the current from M2. Finally, the differential current from M1 and M2 multiplied by the output resistance of the input stage gives the single-ended output voltage, which is the part of the input to the next stage. The bias current of the input differential pair is furnished by M5 (figure 2) [4].
• Common Source Second Gain Stage: The second stage is a current sink load inverter. The motive of the second gain stage is to provide additional gain consisting of transistors M6 and M7. This stage receives the output from the drain of M2 and amplifies it through M6 by common source configuration. This stage is equipped with an active device, M7, which serve as the load resistance for M6. The gain of this stage is the trans-conductance of M6 times the equivalent load resistance seen at the output of M6 and M7. M6 is the driver while M7 acts as load. The bias current of the second stage is provided by M7. This stage provides voltage gain and high output resistance.
• Biasing Circuit: A simple resistor divider circuit is used to apply bias voltage to gate of M9
Figure 2. Circuit diagram of an OPAMP Buffer
• Equations
Firstly, choose the device length which will keep the channel modulation parameter constant and give good matching
for current mirrors. L1 =L2 =480nm; L3 =L4= 480nm; L5 =L8= 360nm; L6 =L7 =L9= 120nm; W9= 160nm.
From the desired phase margin, choose the minimum value for Cc, i.e. for a 60° phase margin we use the following relationship. This assumes that z ≥ 10GB (Cc > (2.2/10) CL).
We choose:
Cc= 2.5*0.22*CL
Or CL = 1.25 pF
Cc = 0.6875 pF
Secondly, determine the minimum value for the “tail current” (I5) from the largest of the two values.
I5 = SR. Cc (1)
Eq (1)
I3 = I4= I5 /2
As the same way we will calculate the others parameters using these equations:
S3= (W / L) 3= I5 / (K‘3) [VDD−Vin(max)−∣VT03∣(max)+VT1(min)]2 (2)
S3 = S4
gm1 = GB* Cc (3)
gm2 = gm1
S2 = (g m2) 2 / K \’2 I 5
S 1=S2
VDS5 (sat) =Vin(min)−VSS−I 5β1−VT1(max) (4)
B. D-Flip Flop
• The edge-triggered flip flop is composed of two D-type level-triggered latches. Each Latch have tow transmission gates and tow inverters. Both latches are enabled with complementary clock signal: The second slave latch is driving by the clock signal, while the master latch is enabled by the complemented clock. The master latch is transparent whilst the clock signal is low, and the current value of the D input is propagated to the input of the slave latch. Now, the input transmission-gate of the slave latch is non-conducting. thus, the flip flop stores its current value (figure 3).
Figure 3. Circuit diagram of a D-Flip Flop
• On the rising edge of the input clock, the input transmission-gate of the master latch turn into non-conducting, while the feedback transmission-gate of the master latch becomes conducting. That is, the master latch stores its current value, the value it had immediately before the rising-edge of the clock signal. simultaneously, the slave latch becomes transparent (its input transmission-gate is now conducting) and therefore outputs the value stored in the master latch. The new output value reaches the Q output about three transistor delays (slave input t-gate, two inverter stages) after the rising edge of the clock signal.
• When the clock signal becomes low again, the input transmission-gate of the slave latch turn into non-conducting, while the feedback transmission-gate becomes conducting i.e. the slave latch keeps storing its current value, the value loaded during the preceding rising-edge of the clock signal into the master latch. Simultaneously, the master latch turns into transparent again and the D input value is propagated through the master latch onto the (now non-conducting) input transmission-gate of the slave latch [6].
C. Control Signals Logic
• Analog switch multiplexer here is a (8: 1) MUX, to which corresponding voltage from Resistor String is applied as inputs and control signals from Control Logic Signal is applied a select signals. It is designed using 14 Transmission Gates, where 2 Transmissions gates together acts as (2: 1) MUX. It has 1st Stage composed of 8 (2:1) MUX\’s controlled by B0 and ~B0. The intermediate stage constitutes of 4(2: 1) MUX\’s controlled by B1 and ~B2.
The last stage designed using 2 (2: 1) MUX\’s, which outputs a multiplexed signal (figure 4).
Figure 4. Circuit diagram of a control signals logic
D. Resistor String Ladder
• The design approach follows, determination of suitable R value for the DAC, based on which Width and Length of resistor is decided. The \”W\” and \”L\” values determine the mismatch factor for the Resistor String (figure 5). With R= 1.8109 KΩ, W= 2.6 um, L= 5.1 um and Mismatch Factor = 0.018.
Figure 5. Circuit diagram of the resistor string ladder
III. SIMULATION RESULTS
The performance of the DAC has been evaluated by SPECTRE simulations. Moreover, the results have been checked for a nominal 1.3 V analog power supply.
The static performances of DAC in DNL and INL are 00034LSB and 00026LSB, respectively, as shown in figure 6.
Figure 6. DNL & INL Simulation
The layout of the DAC is shown in figure 7 and it has been designed using a 130-nm CMOS technology. It occupies an active area of 62.415um* 38.64um.
The results, this DAC has one of the best power efficiencies of published work. Moreover, it achieves the lowest power consumption and a high speed, also this DAC has a smallest active area.
Figure 7. Resistor String DAC Layout
IV. CONCLUSION
A low cost, low size and low power effective 3-bit Resistor String DAC has been designed and implemented in 130 nm CMOS process. As expected the simulation results show that the proposed DAC has the following characteristics:
The measured integral nonlinearity (INL) is ±0.00026LSB, the measured differential nonlinearity (DNL) is ± 0.00034LSB and settling time less than 19.82 ns. The layout occupies a small active area of 32.80um x 46.90um in CMOS 130nm.
ACKNOWLEDGMENT
This work was supported by: The National Center of Scientific and Technical Research (CNRST Morocco) under the PPR2 program.
REFERENCES
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